EVAL-AD1852EB【PDF 3/14 页】24-Bit Stereo DAC Evaluation Board

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EVAL-AD1852EB

–3–

SWITCH AND JUMPER FUNCTIONS

S1 is used to select between the RCA SPDIF INPUT (J1) and

the TOSLINK optical input, (U1). The SPDIF signal is a

self-clocking, Manchester-encoded signal that is decoded by

the digital interface receiver (DIR, U2) to extract the left and

right digital audio data and associated status signals.

S2 is used to activate the AD1852 MUTE hardware function.

S3 switches the CPLD (U4) digital input signals between the

digital interface receiver (DIR, U2) and the EXT DATA

INTERFACE (J2). The CPLD (U4) digital outputs go directly

to the AD1852 DAC. In addition to the digital audio data

signals, S3 also switches the master clock between the DIR

(U2) and the Ext Data I/F input (J2) via the NAND gate (U11).

S4 is used to enable the internal AD1852 DEEMPHASIS

digital filter. This is confirmed by lighting the DEEMPH

LED, (DS3).

S5 selects the serial interface modes for the SPDIF receiver

(U2) and the AD1852 DAC (U3):

Table II. Serial Interface Mode Selection

Position

AD1852 Serial Interface Mode

IDPM1

IDPM0

Left Justified, 16 to 24 Bits

S, 16 to 24 Bits

Right Justified, (U2 (DIR) is

set for 24 Bits. Program the

AD1852 via the SPI port for

24 Bits if using U2).

DSP Word Sync, 16- to 24-Bits

Serial Mode is set through SPI

Port using LabView Software.

Spare – Not Used

S6 provides a RESET function via reset generator U8

(ADM811TART) and a “clean” 200 ms delay after release.

U8 also provides a 200 ms delayed reset release at power-up.

This ensures that the digital interface receiver (DIR, U2) and

the AD1852 are correctly initialized after power-up and their

internal registers are set to the correct default values.

JP1 Header is used to select the internal interpolation ratio for

the AD1852. Jumpers are selected according to the following

table. The default is 8

interpolation, i.e., both jumpers are

installed. NOTE: When the internal registers are used, the

effective logic state is the logical OR of the external pin and

the program register, hence both jumpers should be in place

so that the programmable registers can correctly set the state

of the control bits.

Table III.

Interpolation Ratio (SR)

(32 kHz to 50 kHz)

(64 kHz to 100 kHz)

(128 kHz to 200 kHz)

Not Allowed

96/

(JP1-1)

192/

(JP1-2)

Note: 0 = Closed.

Indicator Display LEDs

Five red LED indicators are provided for status indication.

Display LEDs DS1, ZL and DS2, ZR show that the AD1852

is detecting a zero signal in either the left or right channel

respectively.

Display LED DS3, DEEMPH, indicates that either switch S4

has selected de-emphasis or that the incoming SPDIF signal

has the EMPHASIS status bit set. In either case, illumination

of DS3 indicates that the DEEMPHASIS filter function of the

AD1852 is active.

Display LED DS4, VERF, indicates that the digital interface

receiver has detected an error condition in the received SPDIF

signal or the SPDIF Invalid status bit has been set.

Display LED DS5, POWER, shows the presence of 5 V dc on

the analog 5 V power supply.

INTEGRATED CIRCUIT FUNCTIONS

There are 11 active devices on the AD1852 evaluation board.

Following is a brief description of the function of each part.

U1 (TORX173) is the Toshiba Digital Audio Optical

(TOSLink) Receiver. This part accepts a visible red SPDIF-

modulated signal and converts it to a standard TTL digital

signal suitable for input to the digital audio receiver (U2).

U2 (CS8414-CS) digital audio interface receiver, (DIR) receives

and decodes the serial SPDIF, digital audio encoded signal.

This signal is Manchester modulated and is self-clocked at a

multiple of the encoded SPDIF sample rate. Four digital

audio signals are decoded by the CS8414. The serial data

SDATA, the master clock at 256 F

, MCLK, the left/right

frame clock L/

CLK and the serial bit clock at 64 F

, BCLK.

U3 (AD1852JRS) is the high performance stereo DAC.

Depending upon selected modes of operation, (JP1) sample

rates up to 192 kHz and 24 bits may be tested by changing the

internal interpolation ratio. The interface mode can be selected

for Left Justified (LJ), I

S or Right Justified (RJ) by means of

the Interface Mode switch (S5). Internal registers of the

AD1852 can be programmed via the PC Port (J5) or via the

SPI Control Port, header (J3). Mute is controlled directly by

the control switch S2. The De-emphasis filter can be turned

on with the switch DEEMPH (S4) or pre-emphasis may be

detected and enabled by the SPDIF receiver.

U4 (M4-64/32) is a Vantis CPLD and has been programmed

to provides input signal MUX selection, LED buffering and

switch decoding for the different interface modes. The output

interface mode of the DIR (U2) must be compatible with the

input to the AD1852 (U3) and this is selected at the same

time as the mode for the AD1852 is selected, with switch

Interface Mode (S5). S5 is decoded to drive the DIR mode

pins (M0-3) and AD1852 mode pins (IDPM0) and (IDMP1).

The source code in included in Appendix A. Note: Because of

excessive jitter degradation in CPLDs, a separate IC (U11) is

used to select the MCLK input to the AD1852.

U5 (74HC14) provides Schmitt trigger buffering for the SPI

Control Port (J3) and PC Port (J5) signals. This helps to

reduce problems due to noise and ringing on the signal lines.

U6 (LM317) provides 5 V dc low voltage regulation for the

digital section of the evaluation board.

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